FPGA-Accelerated ϵ-Greedy Ant Colony Optimisation for Maritime Bearings-Only Nonlinear Target Motion Analysis

Bearings-Only Target Motion Analysis (BOTMA) is challenging due to nonlinear dynamics, noisy angle-only sensing, and the nonconvexity of maximum-likelihood estimation (MLE). We present a System-on-Chip (SoC) Field-programmable gate array (FPGA) implementation of an Ant Colony Optimisation (ACO) that solves the BOTMA–MLE problem under nonlinear target-motion models in real time. Specifically, we consider an ϵ -greedy ACO ( ϵG-ACO), where with probability 1 - ϵ the next component is selected according to pheromone-guided probabilities, while with probability ϵ it is chosen uniformly at random, thus balancing exploitation and exploration. The design targets a PYNQ-Z1 board (AMD Zynq-7000), where a high-level synthesis (HLS)-generated ACO intellectual property (IP) core communicates with the ARM processing system via Advanced eXtensible Interface (AXI) direct memory access (DMA) and AXI-Stream, enabling high-throughput, low-latency evaluation of candidate solutions. We validate the approach on synthetic trajectories (constant velocity, constant acceleration, and constant jerk) and on a real-world track based on Automatic Identification System (AIS) data, considering a number of parameters for the ship motion ranging from four to eight. Across all cases, the FPGA solution attains estimation accuracy comparable to Python and C++ baselines while dramatically reducing runtime: up to about x 119 over a C++ implementation and up to x 2281 over a Python implementation on a machine equipped with a Silicon M4 Pro 14-core CPU and 24 GB of unified RAM. On-chip power for the 8-parameter implementation is approximately 2.47 W, with the processing system dominating the dynamic power. The design fits comfortably on the XC7Z020 device, utilising about 56% of look-up tables (LUTs), 21% of block RAM (BRAM), and 85% of digital signal processors (DSPs), leaving headroom for future extensions. These results show that coupling metaheuristic optimisation with SoC-FPGA acceleration is a practical route to real-time BOTMA under realistic, nonlinear motion, particularly in resource-constrained embedded settings.